verilog - How to alternate two always blocks? -

i'd design simple verilog code, contains 2 blocks, executing alternatively, handshake. want use 2 flags, do_a , do_b control 2 blocks, block_a , block_b. expected result must ababab... there way correct following code? helping me.

    module tb;     reg clock, reset, do_a, do_b;      initial begin clock = 0; reset = 0; #50; reset = 150; #50; reset = 0; end     #50 clock = ~clock;      @(posedge clock) begin: block_a         if (reset) do_b <= 0;         else if (do_a) begin             do_b <= 0;             $display("a");         end      end      @(posedge clock) begin:block_b         if (reset) do_a <= 1;         else if (do_b) begin             do_a <= 0;             $display("b");         end      end endmodule 

thanks vesiliy, following codes work desired results.

always @(posedge clock) begin: block_a         if (reset) do_b = 0;         else if (do_a) begin             do_b = 0;             $display("a");         end          else do_b <= 1;     end      @(posedge clock) begin:block_b         if (reset) do_a = 1;         else if (do_b) begin             do_a = 1;             $display("b");         end          else do_a <= 0; 

it seems weird, works well.

first of reset = 150; looks strange (typo?). works in context, though.

you have typo in first sequential always - (seemingly) meant write is:

else if (do_a) begin     do_b <= 1;     $display("a"); end  

however, believe main issue here not have else (default) clauses in sequential always blocks.

look @ block (for example):

always @(posedge clock) begin:block_b     if (reset) do_a <= 1;     else if (do_b) begin         do_a <= 0;         $display("b");     end  end 

after reset deasserted do_a = 1; then, assuming fixed previous typo, do_b become 1 lead do_a becoming 0. after state reached, do_a stuck @ 0 until reset everything.

the following addition should fix (the same first always block):

always @(posedge clock) begin:block_b     if (reset) do_a <= 1;     else if (do_b) begin         do_a <= 0;         $display("b");     end     else do_a <= 1;  end 

i believe code above fixes work, however, right way describe functionality implement (simple) state-machine 2 states. google it.