fpga - Process pipelining in VHDL? -

for past few days have been searching method of writing bit of vhdl project allow me trigger processing of set of data , transmit results. device using can begin collect second set of data while simultaneously serving complete first set fpga transmit, , want take advantage of via pipelining haven't been successful.

to trigger collection need send specific set of signals in specific order. after few clock cycles , signal fpga, complete set output on several ports device. goal whole process started simple input pulse, , possible second pulse occur while assignments first pulse still occuring. there way me send first set of signals, , later signal output data while simultaneously sending first set of signals second collection, if makes sense?

here's picture of mean.

(clickable)

as can see, data integration 1 sent during second , third integration stage. load_pulse signal requests data output on data, , can occur later while second set of signals integration 2 sent.

here's bit of test vhdl wrote see if possible simple process:

library ieee; use ieee.std_logic_1164.all;  entity test     port(         x : in std_logic;         y : out std_logic := '0';         z : out std_logic := '0'     ); end test;  architecture test_behav of test begin      process(x)     begin          y <= '0', '1' after 10 ns, '0' after 20 ns;         z <= '0', '1' after 30 ns, '0' after 40 ns;      end process; end test_behav;  library ieee; use ieee.std_logic_1164.all;  entity testbench end testbench;  architecture testbench_behav of testbench      component test         port(             x : in std_logic;             y : out std_logic;             z : out std_logic         );     end component test;      signal x : std_logic := '0';     signal y : std_logic := '0';     signal z : std_logic := '0';  begin      testo: component test         port map(             x => x,             y => y,             z => z         );      x <= '1' after 25 ns;  end testbench_behav; 

in example, trigger process while signal assignments still executing. result here original signal assignments interrupted , new signal assignments completed after x <= '1' after 25 ns, can see here:

(clickable)

is there way accomplish can explain me or point me explanation of, or need take approach?

thanks